module top; integer ic,ia,ib,id;
reg a,b,c,d;
wire cout;
not n1(A,a);
not n2(B,b);
not n3(C,c);
not n4(D,d);
and a1(s1,A,c,D);
and a2(s2,b,C,d);
and a3(s3,a,b,C);
and a4(s4,a,b,d);
and a5(s5,a,C,d);
or r1(cout,s1,s2,s3,s4,s5);
initial
begin
for(ia=0;ia<=1;ia=ia+1)
begin
a=ia;
for(ib=0;ib<=1;ib=ib+1)
begin
b=ib;
begin
for(ic=0;ic<=1;ic=ic+1)
begin
c=ic;
for(id=0;id<=1;id=id+1)
begin
d=id;
#10 $display("a=%d b=%d c=%d d=%d cout=%d",a,b,c,d,cout);
end
end
end
end
end
end
endmodule

module top; integer ic,ia,ib,id;
reg a,b,c,d; wire cout;
not n1(A,a);
not n2(B,b);
not n3(C,c);
not n4(D,d);
and a1(s1,c,d);
and a2(s2,a,b,d);
and a3(s3,A,B,d);
and a4(s4,A,b,C,D);
and a5(s5,a,B,c);
or r1(cout,s1,s2,s3,s4,s5);
initial begin for(ia=0;ia<=1;ia=ia+1)
begin a=ia; for(ib=0;ib<=1;ib=ib+1)
begin b=ib;
begin
for(ic=0;ic<=1;ic=ic+1)
begin c=ic;
for(id=0;id<=1;id=id+1)
begin d=id;

module top;
reg A,B;
wire D;
and_f n1(C,A,B);
not_f n1(D,C);

initial begin
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b1;
#10 A=1'b0;B=1'b1;
#10 A=1'b0;B=1'b0;
#10$finish;
end
endmodule


module and_f(C,A,B);
input A,B;
output C;
nand(C,A,B);
specify
specparam
tpd_0_1=3.0:3.0:3.0,
tpd_1_0=3.0:3.0:3.0;
(A=>C)=(tpd_0_1,tpd_1_0);
(B=>C)=(tpd_0_1,tpd_1_0);
endspecify
endmodule



module not_f(D,C);
input C;
output D;
not(D,C);
specify
specparam
tpd_0_1=2.0:2.0:2.0,
tpd_1_0=2.0:2.0:2.0;
(C=>D)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

module top;
reg A,B;
wire D;
nand_f n1(C,A,B);
not_f n1(D,C);

initial begin
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b1;
#2 A=1'b0;
#10$finish;
end
endmodule


module nand_f(C,A,B);
input A,B;
output C;
nand(C,A,B);
specify
specparam
tpd_0_1=3.0:3.0:3.0,
tpd_1_0=3.0:3.0:3.0;
(A=>C)=(tpd_0_1,tpd_1_0);
(B=>C)=(tpd_0_1,tpd_1_0);
endspecify
endmodule


module not_f(D,C);
input C;
output D;
not(D,C);
specify
specparam
tpd_0_1=2.0:2.0:2.0,
tpd_1_0=2.0:2.0:2.0;
(C=>D)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

module top;
wire o,a1;

system_clk #100 clk2(a1);
nanf201 c1 (o,a1);
endmodule

module nanf201(o,a1);
input a1;
output o;
not(o,a1);
specify
specparam
tpd_0_1=1.13:3.09:7.75,
tpd_1_0=0.93:2.5:7.34;
(a1=>o)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(49*period/50)clk=~clk;
#(period-49*period/50)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
wire [3:0] x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_algo c1 (y_out,x_in);
endmodule
module and4_algo(y_out,x_in);

input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always @(x_in)
begin :and_loop
y_out=0;
for (k=0;k<=3;k=k+1)
if (x_in[k]==1)
begin
y_out=1;
disable and_loop;
end
end
endmodule
module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
wire [3:0] x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_algo c1 (y_out,x_in);
endmodule
module and4_algo(y_out,x_in);

input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always @(x_in)
begin :and_loop
y_out=1;
for (k=0;k<=3;k=k+1)
if (x_in[k] == 0)
begin
y_out = 0;
disable and_loop;
end
end
endmodule
module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
wire [3:0] x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_rtl c1 (y_out,x_in);
endmodule

module and4_rtl(y_out,x_in);
input [3:0] x_in;
output y_out;
assign y_out=&x_in;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
wire x_in1,x_in2,x_in3,x_in4;
system_clk #50 clk1(x_in1);
system_clk #100 clk2(x_in2);
system_clk #200 clk3(x_in3);
system_clk #400 clk4(x_in4);
and4_rtl c1 (y_out,x_in1,x_in2,x_in3,x_in4);
endmodule

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
wire A1,A0,B1,B0;
system_clk #50 clk1(B0);
system_clk #100 clk2(B1);
system_clk #200 clk3(A0);
system_clk #400 clk4(A1);
comparator c1 (A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
endmodule

module comparator(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B = (~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B = A1&(~B1)A0&(~B1)&(~B0)A1&A0&(~B0);
assign A_eq_B = (~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&(~B0)A1&A0&B1&(~B0)A1&(~A0)&B1&(~B0);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

module top;
integer icin,ia,ib;
reg a,b,cin;
wire cout,s;
xor x1(s1,a,b);
and a1(c1,a,b);
xor x2(s,s1,cin);
and a2(c2,s1,cin);
xor x2(cout,c2,c1);
initial
begin
for(ia=0;ia<=1;ia=ia+1)
begin
cin=ia;
for(ib=0;ib<=1;ib=ib+1)
begin
a=ib;
begin
for(icin=0;icin<=1;icin=icin+1)
begin
b=icin;
#10 $display("a=%d b=%d cin=%d s=%d cout=%d",a,b,cin,s,cout);
end
end
end
end
end
endmodule

10/4 作業

module top;
integer ia,ib;
reg a,b;
wire c,s;
and a1(c,a,b);
xor x1(s,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1) begin a=ia; for(ib=0;ib<=1;ib=ib+1) begin b=ib; #10 $display("a=%d b=%d c=%d s=%d",a,b,c,s); end end end endmodule