10/4 作業

module top;
integer ia,ib;
reg a,b;
wire c,s;
and a1(c,a,b);
xor x1(s,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1) begin a=ia; for(ib=0;ib<=1;ib=ib+1) begin b=ib; #10 $display("a=%d b=%d c=%d s=%d",a,b,c,s); end end end endmodule